{"id":7566,"date":"2026-08-01T00:39:50","date_gmt":"2026-07-31T16:39:50","guid":{"rendered":"https:\/\/i007.cc\/wordpress\/?p=7566"},"modified":"2026-08-01T00:39:50","modified_gmt":"2026-07-31T16:39:50","slug":"%e5%8f%91%e7%8e%b0%e6%97%a0%e9%94%81%e9%98%9f%e5%88%97%e5%9c%a8%e6%9f%90%e4%ba%9b%e6%9c%ba%e5%99%a8%e4%b8%8a%e8%bf%90%e8%a1%8c%e7%9a%84%e6%97%b6%e5%80%99%e5%b9%b6%e4%b8%8d%e8%83%bd%e4%bf%9d%e8%af%81","status":"publish","type":"post","link":"https:\/\/i007.cc\/wordpress\/archives\/7566","title":{"rendered":"\u53d1\u73b0\u65e0\u9501\u961f\u5217\u5728\u67d0\u4e9b\u673a\u5668\u4e0a\u8fd0\u884c\u7684\u65f6\u5019\u5e76\u4e0d\u80fd\u4fdd\u8bc1\u987a\u5e8f\uff0c\u53ef\u80fd\u662f\u4ec0\u4e48\u95ee\u9898\uff1f"},"content":{"rendered":"
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\u8fd9\u662f\u4e00\u4e2a\u975e\u5e38\u5178\u578b\u7684\u771f\u5b9e Bug\uff0c\u6839\u672c\u539f\u56e0\u51e0\u4e4e\u53ef\u4ee5\u786e\u5b9a\u662f\u00a0Memory Order \u8bbe\u7f6e\u9519\u8bef<\/strong>\uff0c\u914d\u5408\u4e0d\u540c CPU \u67b6\u6784\u7684\u5185\u5b58\u6a21\u578b\u5dee\u5f02\u624d\u66b4\u9732\u51fa\u6765\u3002<\/p>\n

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\u5148\u7406\u89e3\uff1a\u4e3a\u4ec0\u4e48”\u67d0\u4e9b\u673a\u5668”\u624d\u51fa\u95ee\u9898<\/h3>\n

\u4e0d\u540c CPU \u67b6\u6784\u5bf9\u5185\u5b58\u64cd\u4f5c\u7684\u5141\u8bb8\u91cd\u6392\u7a0b\u5ea6\u5b8c\u5168\u4e0d\u540c\uff1a<\/p>\n

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x86\/x64  \u2192 TSO\uff08Total Store Order\uff09\r\n  \u5141\u8bb8\u7684\u91cd\u6392\uff1a\u53ea\u6709 StoreLoad\uff08\u5199\u540e\u8bfb\u53ef\u4ee5\u88ab\u91cd\u6392\uff09\r\n  \u4e0d\u5141\u8bb8\uff1aStoreStore\u3001LoadLoad\u3001LoadStore\r\n\r\nARM \/ ARM64 \u2192 \u5f31\u5185\u5b58\u6a21\u578b\uff08Weakly Ordered\uff09\r\n  \u51e0\u4e4e\u6240\u6709\u91cd\u6392\u90fd\u5141\u8bb8\uff1a\r\n  StoreStore\uff08\u5199-\u5199\u53ef\u4ee5\u88ab\u91cd\u6392\uff09\u2190 \u8fd9\u662f\u9501-free queue \u6700\u5e38\u8e29\u7684\u5751\r\n  LoadLoad\r\n  LoadStore\r\n  StoreLoad\r\n\r\nPowerPC \u2192 \u6bd4 ARM \u8fd8\u5f31<\/pre>\n
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\u7ed3\u8bba<\/strong>\uff1a\u7528\u00a0relaxed<\/code>\u00a0\u6216\u8005\u9519\u8bef\u7684\u00a0memory_order<\/code>\u00a0\u5199\u51fa\u6765\u7684\u65e0\u9501\u961f\u5217\uff0c\u5728 x86 \u4e0a\u53ef\u80fd\u6070\u597d\u6b63\u786e\uff08x86 \u786c\u4ef6\u5e2e\u4f60\u8865\u4e86\u5f88\u591a barrier\uff09\uff0c\u653e\u5230 ARM \u670d\u52a1\u5668\u6216\u624b\u673a SoC \u4e0a\u5c31\u5f00\u59cb\u51fa\u95ee\u9898\u3002\u8fd9\u4e5f\u662f\u4e3a\u4ec0\u4e48\u5f88\u591a Bug \u5728\u5f00\u53d1\u673a\uff08x86\uff09\u4e0a\u6d4b\u4e0d\u51fa\u6765\uff0c\u4e0a\u7ebf\uff08ARM\uff09\u624d\u66b4\u9732\u3002<\/p>\n
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\u6700\u5e38\u89c1\u7684\u5177\u4f53 Bug\uff1aSPSC Queue \u91cc\u7684 StoreStore \u91cd\u6392<\/h3>\n
\u56de\u5230\u4e4b\u524d\u5199\u7684 SPSC Queue\uff0c\u770b\u8fd9\u4e2a\u7248\u672c\uff1a<\/p>\n
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\/\/ \u9519\u8bef\u7248\u672c\uff1atail \u7528\u4e86 relaxed\r\nbool push(const T& item) {\r\n    size_t tail = tail_.load(std::memory_order_relaxed);\r\n    size_t next = (tail + 1) & MASK;\r\n    if (next == head_.load(std::memory_order_acquire))\r\n        return false;\r\n\r\n    buffer_[tail] = item;                          \/\/ \u2460 \u5199\u6570\u636e\r\n\r\n    tail_.store(next, std::memory_order_relaxed);  \/\/ \u2461 \u66f4\u65b0 tail\uff08BUG\uff1arelaxed\uff09\r\n    return true;\r\n}\r\n\r\nbool pop(T& item) {\r\n    size_t head = head_.load(std::memory_order_relaxed);\r\n    if (head == tail_.load(std::memory_order_relaxed))  \/\/ \u2462 \u8bfb tail\uff08BUG\uff1arelaxed\uff09\r\n        return false;\r\n\r\n    item = buffer_[head];                          \/\/ \u2463 \u8bfb\u6570\u636e\r\n\r\n    head_.store((head + 1) & MASK, std::memory_order_release);\r\n    return true;\r\n}<\/pre>\n
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\u5728 ARM \u4e0a\u7684\u95ee\u9898\u65f6\u95f4\u7ebf\uff1a<\/p>\n
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Producer\uff08\u6838\u5fc30\uff09         Consumer\uff08\u6838\u5fc31\uff09\r\n\r\n\u2460 buffer_[tail] = item   \r\n\u2461 tail_.store(next)      \r\n                          \u2462 \u770b\u5230 tail \u66f4\u65b0\u4e86\uff08tail != head\uff09\r\n                          \u2463 \u8bfb buffer_[head]\r\n                             \u2190 \u8bfb\u5230\u7684\u662f\u65e7\u6570\u636e\u6216\u5783\u573e\u503c\uff01\r\n\r\n\u539f\u56e0\uff1aARM \u5141\u8bb8 StoreStore \u91cd\u6392\r\nCPU \u5b9e\u9645\u6267\u884c\u987a\u5e8f\u53ef\u80fd\u662f\uff1a\r\n  \u2461 tail_.store(next)    \u2190 \u5148\u628a tail \u5199\u5230\u5176\u4ed6\u6838\u53ef\u89c1\r\n  \u2460 buffer_[tail] = item \u2190 \u6570\u636e\u5199\u5165\u8fd8\u6ca1\u4f20\u64ad\u8fc7\u53bb<\/pre>\n
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Consumer \u770b\u5230\u00a0tail<\/code>\u00a0\u5df2\u7ecf\u66f4\u65b0\uff0c\u4ee5\u4e3a\u6570\u636e\u51c6\u5907\u597d\u4e86\uff0c\u5b9e\u9645\u4e0a\u6570\u636e\u5199\u5165\u8fd8\u6ca1\u6709\u4f20\u64ad\u5230\u81ea\u5df1\u7684 cache\u3002<\/p>\n
\u6b63\u786e\u5199\u6cd5<\/strong>\uff1a<\/p>\n
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Producer\uff08\u6838\u5fc30\uff09         Consumer\uff08\u6838\u5fc31\uff09\r\n\r\n\u2460 buffer_[tail] = item   \r\n\u2461 tail_.store(next)      \r\n                          \u2462 \u770b\u5230 tail \u66f4\u65b0\u4e86\uff08tail != head\uff09\r\n                          \u2463 \u8bfb buffer_[head]\r\n                             \u2190 \u8bfb\u5230\u7684\u662f\u65e7\u6570\u636e\u6216\u5783\u573e\u503c\uff01\r\n\r\n\u539f\u56e0\uff1aARM \u5141\u8bb8 StoreStore \u91cd\u6392\r\nCPU \u5b9e\u9645\u6267\u884c\u987a\u5e8f\u53ef\u80fd\u662f\uff1a\r\n  \u2461 tail_.store(next)    \u2190 \u5148\u628a tail \u5199\u5230\u5176\u4ed6\u6838\u53ef\u89c1\r\n  \u2460 buffer_[tail] = item \u2190 \u6570\u636e\u5199\u5165\u8fd8\u6ca1\u4f20\u64ad\u8fc7\u53bb<\/pre>\n
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\/\/ acquire \u8bed\u4e49\uff1a\u4fdd\u8bc1\u6b64\u884c\u4e4b\u540e\u7684\u6240\u6709\u8bfb\u53d6\uff08\u5305\u62ec buffer_ \u7684\u8bfb\uff09\r\n\/\/ \u80fd\u770b\u5230\u914d\u5bf9 release \u4e4b\u524d\u7684\u6240\u6709\u5199\u5165\r\nif (head == tail_.load(std::memory_order_acquire))  \/\/ \u2705\r\n    return false;\r\n\r\nitem = buffer_[head];  \/\/ \u73b0\u5728\u4fdd\u8bc1\u80fd\u8bfb\u5230\u6b63\u786e\u6570\u636e<\/pre>\n
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Acquire-Release \u7684\u672c\u8d28\uff1a\u5efa\u7acb happens-before \u5173\u7cfb<\/h3>\n
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Producer:\r\n  buffer_[tail] = item;              \u2500\u2510\r\n  tail_.store(next, release);         \u2518 release\uff1a\u8fd9\u4e24\u884c\u6709\u5148\u540e\u987a\u5e8f\uff0c\u4e14\u5bf9\u5916\u53ef\u89c1\r\n\r\n                    \u2195  synchronizes-with\uff08\u8de8\u7ebf\u7a0b\u7684 happens-before\uff09\r\n\r\nConsumer:\r\n  tail_.load(acquire);               \u2500\u2510\r\n  item = buffer_[head];              \u2500\u2518 acquire\uff1a\u8fd9\u4e24\u884c\u6709\u5148\u540e\u987a\u5e8f\uff0c\u4e14\u80fd\u770b\u5230\u4e0a\u9762\u7684\u5199<\/pre>\n
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release + acquire<\/code>\u00a0\u914d\u5bf9\u521b\u5efa\u4e86\u4e00\u4e2a\u8de8\u7ebf\u7a0b\u7684\u540c\u6b65\u70b9<\/strong>\uff1a\u4efb\u4f55\u5728 release store \u4e4b\u524d\u7684\u5199\u5165\uff0c\u5bf9\u6267\u884c\u4e86\u5bf9\u5e94 acquire load \u7684\u7ebf\u7a0b\u90fd\u662f\u53ef\u89c1\u7684\u3002<\/p>\n
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MS Queue \u91cc\u66f4\u9690\u853d\u7684 Memory Order \u9519\u8bef<\/h3>\n
\u591a\u751f\u4ea7\u8005\u591a\u6d88\u8d39\u8005\u7684 Michael-Scott Queue \u91cc\uff0cCAS \u7684 memory order \u540c\u6837\u5bb9\u6613\u5199\u9519\uff1a<\/p>\n
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\/\/ \u9519\u8bef\uff1aCAS \u6210\u529f\u65f6\u7528 relaxed\r\nif (tail->next.compare_exchange_weak(\r\n        next, node,\r\n        std::memory_order_relaxed,   \/\/ \u2190 \u6210\u529f\u65f6\u5e94\u8be5\u662f release\r\n        std::memory_order_relaxed)) {\r\n    \/\/ ...\r\n}\r\n\r\n\/\/ \u6b63\u786e\uff1a\r\nif (tail->next.compare_exchange_weak(\r\n        next, node,\r\n        std::memory_order_release,   \/\/ \u6210\u529f\u65f6\uff1a\u53d1\u5e03\u65b0\u8282\u70b9\uff0c\u9700\u8981 release\r\n        std::memory_order_relaxed)) { \/\/ \u5931\u8d25\u65f6\uff1a\u53ea\u662f\u91cd\u8bd5\uff0crelaxed \u591f\u4e86\r\n    \/\/ ...\r\n}\r\n\r\n\/\/ \u51fa\u961f\u65f6\u8bfb\u53d6\u8282\u70b9\u6570\u636e\uff1a\r\nNode* next = head->next.load(std::memory_order_acquire); \/\/ \u9700\u8981 acquire\r\nval = next->data;  \/\/ \u80fd\u770b\u5230\u5165\u961f\u65f6\u5199\u5165\u7684 data<\/pre>\n
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\u6392\u67e5\u6b65\u9aa4<\/h3>\n
\u7b2c\u4e00\u6b65\uff1a\u68c0\u67e5\u6240\u6709 atomic \u64cd\u4f5c\u7684 memory_order<\/strong><\/p>\n
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# \u5feb\u901f\u641c\u7d22\u4ee3\u7801\u91cc\u6240\u6709\u7528\u4e86 relaxed \u7684\u5730\u65b9\r\ngrep -n \"memory_order_relaxed\" your_queue.cpp<\/pre>\n
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\u5bf9\u6bcf\u4e00\u5904\u00a0relaxed<\/code>\u00a0\u95ee\u81ea\u5df1\uff1a\u8fd9\u4e2a\u64cd\u4f5c\u662f\u5426\u9700\u8981\u548c\u5176\u4ed6\u7ebf\u7a0b\u7684\u67d0\u4e2a\u64cd\u4f5c\u540c\u6b65\uff1f\u5982\u679c\u662f\uff0c\u5c31\u9700\u8981\u00a0acquire<\/code>\/release<\/code>\u3002<\/p>\n
\u7b2c\u4e8c\u6b65\uff1a\u753b\u51fa happens-before \u94fe<\/strong><\/p>\n
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\u5bf9\u6bcf\u4e00\u5bf9\"\u5199\u6570\u636e \u2192 \u901a\u77e5 \u2192 \u8bfb\u6570\u636e\"\u7684\u6a21\u5f0f\uff0c\u786e\u8ba4\uff1a\r\n\r\n\u5199\u6570\u636e            store(release)         load(acquire)       \u8bfb\u6570\u636e\r\n\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 \u227a \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 sync \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500 \u227a \u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\u2500\r\n\u5fc5\u987b\u5728 release \u4e4b\u524d        \u8fd9\u91cc\u5efa\u7acb\u540c\u6b65        \u5fc5\u987b\u5728 acquire \u4e4b\u540e<\/pre>\n
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\u5982\u679c\u8fd9\u6761\u94fe\u65ad\u4e86\uff08\u4efb\u4f55\u4e00\u73af\u7528\u4e86\u00a0relaxed<\/code>\uff09\uff0c\u5c31\u662f Bug\u3002<\/p>\n
\u7b2c\u4e09\u6b65\uff1a\u5728 ARM \u4e0a\u52a0\u538b\u6d4b\u8bd5<\/strong><\/p>\n
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\/\/ \u7528 TSan\uff08Thread Sanitizer\uff09\u53ef\u4ee5\u68c0\u6d4b data race\r\n\/\/ \u7f16\u8bd1\u65f6\u52a0 -fsanitize=thread\r\n\r\n\/\/ \u6216\u8005\u5728 ARM \u673a\u5668\u4e0a\u7528 stress \u5de5\u5177\u52a0\u5927\u5e76\u53d1\u538b\u529b\uff1a\r\nfor (int i = 0; i < 1000000; i++) {\r\n    producer_thread();\r\n    consumer_thread();\r\n    assert(consumed_value == produced_value);  \/\/ \u9a8c\u8bc1\u987a\u5e8f\r\n}<\/pre>\n
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\u7b2c\u56db\u6b65\uff1a\u7528 C++ \u6807\u51c6\u4fdd\u8bc1\uff0c\u4e0d\u4f9d\u8d56\u5e73\u53f0\u884c\u4e3a<\/strong><\/p>\n
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\/\/ \u5371\u9669\uff1a\u4f9d\u8d56 x86 \u7684\u5f3a\u5185\u5b58\u6a21\u578b\uff0c\u6362\u5e73\u53f0\u5c31\u51fa Bug\r\nstd::atomic<int> flag{0};\r\nflag.store(1, std::memory_order_relaxed);  \/\/ \u5728 x86 \u4e0a\u6070\u597d\u4e0d\u4f1a\u88ab\u91cd\u6392\r\n\r\n\/\/ \u5b89\u5168\uff1a\u7528\u6807\u51c6\u89c4\u5b9a\u7684 memory order\uff0c\u6240\u6709\u5e73\u53f0\u884c\u4e3a\u4e00\u81f4\r\nflag.store(1, std::memory_order_release);<\/pre>\n
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\u4e00\u4e2a\u68c0\u67e5 memory order \u7684\u601d\u7ef4\u6846\u67b6<\/h3>\n
\u9762\u5bf9\u4efb\u610f\u4e00\u4e2a\u00a0atomic<\/code>\u00a0\u64cd\u4f5c\uff0c\u95ee\u4e09\u4e2a\u95ee\u9898\uff1a<\/p>\n
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1. \u8fd9\u4e2a store \u4e4b\u524d\uff0c\u6709\u6ca1\u6709\u666e\u901a\u5185\u5b58\u5199\u5165\u9700\u8981\u5bf9\u5176\u4ed6\u7ebf\u7a0b\u53ef\u89c1\uff1f\r\n   \u2192 \u5982\u679c\u6709\uff0c\u7528 release\r\n\r\n2. \u8fd9\u4e2a load \u4e4b\u540e\uff0c\u6709\u6ca1\u6709\u666e\u901a\u5185\u5b58\u8bfb\u53d6\u4f9d\u8d56\u4e8e\"\u770b\u5230\u6700\u65b0\u503c\"\uff1f\r\n   \u2192 \u5982\u679c\u6709\uff0c\u7528 acquire\r\n\r\n3. \u8fd9\u4e2a\u64cd\u4f5c\u662f\u5426\u9700\u8981\u5168\u5c40\u987a\u5e8f\u4e00\u81f4\uff08\u6bd4\u5982\u5b9e\u73b0 mutex\uff09\uff1f\r\n   \u2192 \u7528 seq_cst\uff08\u4ee3\u4ef7\u6700\u9ad8\uff0c\u975e\u5fc5\u8981\u4e0d\u7528\uff09\r\n\r\n4. \u4ee5\u4e0a\u90fd\u4e0d\u662f\uff08\u53ea\u662f\u5355\u7eaf\u7684\u8ba1\u6570\u5668\u3001\u7edf\u8ba1\uff09\uff1f\r\n   \u2192 \u624d\u80fd\u7528 relaxed<\/pre>\n
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